When 10:30 AM - 11:30 AM Dec 01, 2017
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Interconnects Beyond Cu


Katayun (Katy) Barmak
Department of Applied Physics and Applied Mathematics, Columbia University

Power consumption by Cu interconnects (i.e., the on-chip metallic wiring) is an issue of critical concern for current CMOS technology. At the 45 nm-node, communications power consumption achieved parity with that of semiconductor operation and this will increase to 79% of the total power at the 7 nm-node. Looking to the future, Cu interconnect technology will continue to be the primary bottleneck, with the majority of the power consumed by the smallest, device level interconnects due to their greater numbers. This is a largely unaddressed problem. While much of the work in the semiconductor community has focused on novel three wire electronic logic devices for increased energy efficiency, the more urgent need for better wires at the device level has only been addressed by incremental improvements. The increased power consumption in Cu interconnects is a consequence of the resistivity size effect, wherein conductors with dimensions near or below the mean free path of electrons (39 nm for Cu at room temperature) exhibit higher resistivity than bulk conductors and thus higher “I2R” losses. The resistivity size effect was first reported by Thompson in 1901. Its importance to Cu interconnects was identified in the 1990s and has been of concern to the semiconductor community since then. In this talk, I will present our studies of the impact of surfaces and grain boundaries on Cu resistivity, and demonstrate the anisotropy of the resistivity size effect in oriented single crystal nanowires of W. In addition, I will discuss the future of interconnects beyond Cu.

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